1. Field of the Invention
The present invention relates to electronic memories and particularly to electrically programmable and erasable memories, particularly EEPROM (Electrically-Erasable Programmable Read-Only Memory) memories and Flash memories (Flash-EEPROM).
The present invention relates to the reading of binary words in such memories and more particularly in serial input/output memories.
2. Description of the Related Art
In EP patent no. 712 133,the applicant has already explained the problem encountered with serial memories, due to the fact that it is almost impossible to provide sense amplifiers adapted to the rates imposed by synchronous-type serial buses. Indeed, the time Tr allowed for a binary word to be read in a serial access memory runs from the instant the last address bit is received by the memory to the instant the first bit of the word designated by said address is sent by the memory.
As an address bit is generally read in the middle of a clock period, and a data bit sent at the start of a clock period, the time Tr is at the minimum equal to half a clock period. In practice, the time Tr is on the order of 1.5 clock periods with an I2C (Inter-Integrated Circuit) type bus (a pause of one clock cycle being allowed between the receipt of the last address bit and the sending of the first bit of the word read), of 1 clock period with a Microwire-type bus, and on the order of 0.5 clock period with an SPI (Serial Peripheral Interface) type bus, which is the worst case as far as memory reading rapidity requirements are concerned.
For a better understanding, a sequence of reading a binary word in a serial memory is shown in FIGS. 1A, 1B, 1C. FIG. 1A represents a clock signal CK applied to the memory, FIG. 1B represents data bits DIN applied to the memory, and FIG. 1C represents the data bits DOUT supplied by the memory. First, the memory receives data bits I7, I6 . . . I0 forming a read instruction (RINST) then bits AN, AN−1, . . . A2, A1, A0 forming the address (AD) of the binary word to be read from the serial memory. The last address bit A0 is received at an instant t1, corresponding to the rising edge of a pulse of the clock signal CK. At an instant t2 corresponding to the falling edge of the same clock pulse (SPI type bus), the first bit D7 of the word read designated by the address received must be supplied as an outgoing datum DOUT. Tr, the read time, is thus equal to t2-t1 and here is equal to half a clock cycle. During time Tr, the address received must be applied to an address decoder of the serial memory, the word designated by the address received (AD) must be read, loaded into an output register with parallel input and serial output, and a shift signal must be applied to the output register so that the first bit D7 of the word read is sent.
Moreover, the clock frequency of serial buses has constantly increased in recent years. Some ten years ago it was on the order of 1 MHz, i.e., a clock period in the order of one microsecond, which would allow a reading time Tr on the order of 0.5 microseconds in the worst case (SPI type bus). It is often on the order of 20 MHz at present, i.e., a clock period of 50 nanoseconds and a short reading time Tr on the order of 25 nanoseconds.
To overcome this disadvantage, EP patent no. 712 133 describes a reading method involving triggering a read operation before all of the address bits have been received, which involves simultaneously reading M binary words having the same partial address (address being received the least significant address bits of which are not yet known). As the address bits are received at the pace of the clock signal, the time saved is equal to the period of the clock signal multiplied by the number N of address bits read ahead.
The disadvantage of this read-ahead method is that it requires providing a greater number of sense amplifier circuits than in a conventional memory. Thus, sixteen sense amplifier circuits instead of eight must be provided for a two-byte read-ahead, thirty-two sense amplifier circuits must be provided instead of eight for a four-byte read-ahead, etc.
In EP patent no. 1 172 820,this problem is identified and a method reducing the number of sense amplifiers required for a read-ahead is proposed. Very schematically, this method involves reading ahead only one part of the binary words having the same partial address. On the other hand, this partial read-ahead method requires a quite complex interlinking of the bit lines in the memory array, so that a same sense amplifier can read two bits of different ranks in the same binary word and two different sense amplifiers can simultaneously read two bits of the same rank of two binary words having identical partial addresses.